L1 cache - traducción al Inglés
![Austek]] A38202; to the right of the processor)](https://commons.wikimedia.org/wiki/Special:FilePath/Motherboard Intel 386.jpg?width=200 "Austek]] A38202; to the right of the processor)")
![[[Motherboard]] of a [[NeXTcube]] computer (1990). At the lower edge of the image left from the middle, there is the CPU [[Motorola 68040]] operated at 25 [[MHz]] with two separate level 1 caches of 4 KiB each on the chip, one for the instructions and one for data. The board has no external L2 cache.](https://commons.wikimedia.org/wiki/Special:FilePath/NeXTcube motherboard.jpg?width=200 "[[Motherboard]] of a [[NeXTcube]] computer (1990). At the lower edge of the image left from the middle, there is the CPU [[Motorola 68040]] operated at 25 [[MHz]] with two separate level 1 caches of 4 KiB each on the chip, one for the instructions and one for data. The board has no external L2 cache.")
общая лексика
Level 1 cache
первичная кэш-память
кэш-память, расположенная на кристалле процессора, в отличие от вторичной кэш-памяти, находящейся обычно в процессорном модуле или на системной плате
синоним
общая лексика
Level 3 cache
кэш-память третьего уровня
дополнительная кэш-память, размещаемая на системной плате между вторичным кэшем и ОЗУ. Этот тип кэш-памяти появился, после того как первичную (L1) и вторичную (L2) кэш-память производители стали встраивать в процессоры
Смотрите также
Wikipedia
A CPU cache is a hardware cache used by the central processing unit (CPU) of a computer to reduce the average cost (time or energy) to access data from the main memory. A cache is a smaller, faster memory, located closer to a processor core, which stores copies of the data from frequently used main memory locations. Most CPUs have a hierarchy of multiple cache levels (L1, L2, often L3, and rarely even L4), with different instruction-specific and data-specific caches at level 1. The cache memory is typically implemented with static random-access memory (SRAM), in modern CPUs by far the largest part of them by chip area, but SRAM is not always used for all levels (of I- or D-cache), or even any level, sometimes some latter or all levels are implemented with eDRAM.
Other types of caches exist (that are not counted towards the "cache size" of the most important caches mentioned above), such as the translation lookaside buffer (TLB) which is part of the memory management unit (MMU) which most CPUs have.
